· Daily Matrices
· DAC Pavilion Panels
· Business Day@DAC
· Search the Program

· Keynotes
· Papers
· Panels
· Special Sessions
· Monday Tutorial
· Friday Tutorials

· Intro to EDA
· Interoperability
· UML for SoC Design
· Women's Workshop

· Structured ASICs
· Power Minimization




MONDAY, June 7, 2004, 12:00 PM - 05:00 PM | Room: 6D

  WORKSHOP
  The Last Interoperability Workshop

  Organizer(s): John Darringer, IBM Corp., Scott Makinen, Hewlett-Packard Co., Scott Peterson, LSI Logic, Rahul Goyal, Intel Corp.

    This year DAC will host the fifth and final Workshop on Interoperability, a subject of perpetual and passionate interest. Since the first meeting in 2000 there has been remarkable progress in advancing interoperability. There is now the Open Access coalition of 23 companies promoting an open standard API and open database implementation, based on technology from Cadence. Synopsys has established an API for accessing their Milkyway data model and there is a GoldenGate project developing a bridge between the two models. A growing number of EDA companies are migrating their tools to these new interfaces to provide customers with much tighter and more efficient coupling of key applications - enabling a major advance in interoperability needed for design systems to keep pace with advancing technology. The scope has widened to include data management, design constraints and even mask development. The Workshop will consist of an update on the movement followed by presentations from industry leading companies on how these efforts address the interoperability challenges facing the electronics industry, and close with a Panel discussion open to your questions.

12:00 Lunch

Introduction
1:00 Welcome - John Darringer, IBM Corp.
1:05 Milkyway Plans and Status - Rich Goldman, Synopsys, Inc.
1:20 Open Access Plans and Status - Scott Peterson, LSI Logic Corp. and Chair: OA Coalition
1:35 Open Access Implementation Status - Joe Santos, Cadence Design Systems, Inc.

Industrial Experience - Chair: Scott Makinen, Hewlett-Packard Co.
1:50 Jim Brewer, Hewlett-Packard Co.
2:00 Kevin Cleerman, LSI Logic Corp.
2:10 Joachim Glas, Infineon Tech.
2:20 Kazuhiko Kobayashi, Renesas Technology Corp.

EDA Vendor Experience - Chair: Rahul Goyal, Intel Corp.
2:30 Michael Buehler Garcia, PDF Solutions, Inc.
2:40 Joe Kwan, Mentor Graphics Corp.
2:50 Venk Shukla, Magma Design Automation, Inc.
3:00 Ivo van Zandoort, Sagantec

3:10 Break

New Directions - Chair: Scott Peterson, LSI Logic Corp.
3:30 Data Management - Joseph Morrell, IBM Corp.
3:40 Timing and Library Representation - Tim Ehrler, Philips Semiconductor
3:50 Golden Gate Bridge - Jim Wilmore, Hewlett-Packard Co. and WG Chair
4:00 Design-to-Mask - Steve Schulz, Si2, Inc.

4:10 Panel: Are We Done?

Chair: Richard Goering, EE Times
- Panelists selected from speakers above

5:00 Adjourn